2011 Rajasthan Technical University B.Tech 5 Semester Computer science & engineering "Computer Architecture" question paper

Question Paper Details:

University:Rajasthan Technical University
Course: B.Tech Computer science & engineering
Subject: Computer Architecture
Exam Year: January 2011
Year or Semester: Third year/ Fifth Semester
Paper Code: 5E3251

Unit-I

1. a) Define control function in register transfer language.What do you understand by bus transfer? Explain with examples. [Marks 8]
    b) Represent the folowing conditional control statement by two register transfer statements with control function.
          if (P=1) then (R1<- R2)
           else if (Q=1) then (R2<- R3)
       Draw bus system for above with three stage device. [Marks 8]

OR

a) Define register transfer language. What do you understand by arithmetic micro operations? Explain with examples? [Marks 8]
b) Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. The circuit generates the following four arithmetic operation in conjunction with the input carry Cin. Draw the logic diagram for the first two stages. [Marks 8]
     
         S           Cin=0                     Cin=1
         o         D=A+B Addition      D=A+1   Increment
         1         D=A-1  Decrement   D=A+B bar +1  Subtraction

Unit-II

2. What is pipelining? What is the maximum speed up that can be attained? Construct an instruction pipeline. Is it possible to attain maximum speed up in an instruction pipeline? [Marks 16]

OR

Write a program to evaluate the arithmetic statement:
 
      X=A-B+C*(D*E-F)/ G+H*K
   a) Using a general register computer with three address instructions.
   b) Using a general register computer with two address instructions.
   c) Using an accumulator type computer with one address instructions.
   d) Using a stack organized computer with zero address operation instructions.  [Marks 4*4=16]

Unit-III

3. a) Design an array multiplier that multiplies a binary number of four bits with a binary number of three bits. [Marks 8]
   b) Explain carry look ahead adder. [Marks 8]

OR

a) Explain Booth’s algorithm for multiplication of signal 2’s complement numbers. [Marks 10]
b) Explain Ripple carry adder. [Marks 6]

Unit-IV

4. a) What is content addressable memory? Describe its design procedure. What is the role of match register. [Marks 10]
   b) Design a 4*3 RAM. Draw the logic circuit of basic cell also. [Marks 6]

OR

a) Explain cache memory and mapping procedures used with cache memory organization. [Marks 10]
b) Explain memory hierarchy in a computer system. [Marks 6]

Unit-V

5. a) How many character per second can be transmitted over a 1200 band line in each of the following modes assuming a character code of eight bits.
     1) Synchronous serial transmission.
     2) Asynchronous serial transmission with 2 stop bits. [Marks 4*2=8]
   b) Explain CPU-IOP communication with a diagram. [Marks 8]

OR

a) Explain the difference between programmed I/O and interrupt initiated I/O giving an example of each. [Marks 8]
 b) What is DMA technique? Explain DMA controller and DMA transfer, with suitable diagram. [Marks 8]