2010 Rajasthan Technical University B.Tech 7 Semester Computer science & engineering "Logic Synthesis" question paper

Question Paper Details:

University:Rajasthan Technical University
Course: B.Tech Computer science & engineering
Subject: Logic Synthesis
Exam Year: January 2010
Year or Semester: Fourth year/ Seventh Semester
Paper Code: 7E4093

Unit-I

a) Explain the four phases in creating macro electronics circuit and compute added synthesis and optimization. [Marks 8]
b) Explain the algorithm review of graph definitions and notations. [Marks 8]

OR

Write short notes on any four:
i) Vertex cover
ii) Graph coloring
iii) Clique covering and partitioning
iv) Asisc and moore’s law
v) Micro electronic design. [Marks 16]

Unit-II

a) Explain the compilation and behavioral techniques. [Marks 6]
b) Explain the circuits specifications for architectural synthesis resources and constraints. [Marks 10]

OR

Write short notes on any four:
i) Data flow and sequencing graphs
ii) Tamporal domain scheduling
iii) Hardware modeling language
iv) Hierarchical models and synchronization
v) Performance estimation resource dominated and general circuits. [Marks 16]

Unit-III

a) Explain the scheduling algorithm latency. [Marks 6]
b) Explain the under timing constraints and relative scheduling with resource constraints integer linear programing model. [Marks 10]

OR

Write short notes an any four:
i) Force directed scheduling
ii) Multiprocessor scheduling
iii) Scheduling constraints and resources
iv) ALAP scheduling
v) Heuristic scheduling algorithms. [Marks 16]

Unit-IV

a) Explain the functions with multi volume inputs and list oriented manipulation. [Marks 10]
b) What are combinational circuits? [Marks 3]
c) What are sequential circuits? [Marks 3]

OR

a) Explain the exact logic minimization and principle for logic optimization. [Marks 8]
b) Explain the testability properties operations on two level logic cover positional cube notation. [Marks 8]

Unit-V
a) Explain the sequential circuit optimization using state based models. [Marks 10]
b) Explain the testability consideration for synchronous circuits. [Marks 6]

OR

a) Explain the sequential circuit optimization using network models. [Marks 10]
b) Explain the implicit finite state machine traversal methods. [Marks 6]